Frequency detector for fast frequency lock of digital PLLs

Introduction: A wide tuning range for a PLL can be achieved by incorporating a frequency-locked loop (FLL) in parallel with the PLL. The key building block of an FLL is the frequency detector (FD) that determines the difference between the oscillator’s divided clock (CKV) and the reference clock (REF). There are many ways to accomplish frequency lock in digital PLLs, but all of them suffer from a major drawback—slow frequency acquisition. In [1] an up– down counter (UPD) triggered by the edges of REF and CKV was used for frequency acquisition. The advantage of this method is that the up–down counter serves not only as a frequency detector but also as an accumulator, and thus it can directly control a digitally controlled oscillator (DCO) without the need for additional hardware. Another way to design an FD is to use two separate counters to count edges of the oscillator’s divided clock and the reference clock [2]. The values in those counters are compared after a certain number of reference periods, which makes it extremely slow. The frequency locking capability can be incorporated into a phase-locked loop by using a phase-frequency detector (PFD) [3]. This approach is simple to implement but also suffers from slow frequency acquisition. In this Letter, a new frequency detector, which allows for fast frequency locking of digital PLLs, is described.